As the name indicates Differential Amplifier is a dc-coupled amplifier that amplifies the difference between two input signals. It is the building block of analog integrated circuits and operational amplifiers (op-amp). One of the important feature of differential amplifier is that it tends to reject or nullify the part of input signals which is common to both inputs. This provides very good noise immunity in a lot of applications. Let’s see the block diagram of a differential amplifier.

V_i1 and V_i2 are input terminals and V_o1 and V_o2 are output terminals with respect to ground. We can feed two input signals at the same time or one at a time. In the former case it is called dual input otherwise it is single input. Similarly there are two ways to take output also. If the output is taken from one terminal with respect to ground, it is unbalanced output or if the output is taken between two output terminals, it is balanced output.

Differential Amplifier using BJT

The simplest form of differential amplifier can be constructed using Bipolar Junction Transistors as shown in the below circuit diagram. It is constructed using two matching transistors in common emitter configuration whose emitters are tied together.

Configurations

Based on the methods of providing input and taking output, differential amplifiers can have four different configurations as below.

1. Single Input Unbalanced Output
2. Single Input Balanced Output
3. Dual Input Unbalanced Output
4. Dual Input Balanced Output

Single Input Unbalanced Output

In this case, only one input signal is given and the output is taken from only one of the two collectors with respect to ground as shown below.

When input signal V_in1 is applied to the transistor Q1, it’s amplified and inverted voltage gets generated at the collector of the transistor Q1. At the same time it’s amplified and non-inverted voltage gets generated at the collector of the transistor Q2 as shown in the above diagram. Unbalanced output will contain unnecessary dc content as it is a dc coupled amplifier therefore this configuration should follow by a level translator circuit.

How the transistor Q2 also producing output voltage even though the input is provided only to transistor Q1 ?

The effect of input voltage V_in1 is coupled to the transistor Q2 via the common emitter resistor R_E. You can see the proof of this in the AC Analysis section.

Single Input Balanced Output

As above only one input signal is given even though the output is taken from both collectors.

This will give us more amplified version of output as it is combining the effect of both transistors. There won’t be any unnecessary dc content in balanced output as the dc contents in both outputs gets canceled each other.

• Vo = Vo1 – Vo2

Dual Input Unbalanced Output

Both inputs are given in this case ie, differential input but the output is taken from only one of the two collectors with respect to ground as shown below.

Amplified version of difference in both signals will be available at the output. The voltage gain is half the gain of the dual input, balanced output differential amplifier. Unbalanced output will contain unnecessary dc content as it is a dc coupled amplifier therefore this configuration should follow by a level translator circuit.

Dual Input Balanced Output

Above circuit consists of two identical transistors Q1 and Q2 with its emitters coupled together. Collectors are connected to main supply VCC through collector resistor Rc. Magnitude of power supplies VCC and –VEE will be same.

• Vo = Ad(V_in1 – V_in2)

Where Ad = differential gain

V_in1, V_in2 = input voltages

When V_in1 = V_in2, obviously the output will be zero. ie, differential amplifier suppresses common mode signals.

For effective operation, components on either sides should be match properly. Input signals are applied at base of each transistor and output is taken from both collector terminals. There won’t be any unnecessary dc content in balanced output as the dc contents in both outputs gets canceled each other.

DC Analysis

DC analysis provides the operating point values I_CQ and V_CEQ for the transistors used in the circuit. The DC equivalent circuit obtained by reducing all AC signals to zero as shown in figure below.

Assume :

• Source Resistance, R_S1 = R_S2 = R_S
• Q1 = Q2
• R_E1 = R_E2 hence R_E = R_E1||R_E2
• R_C1 = R_C2 = R_C
• |VCC|=|VEE|

Applying KVL to base – emitter loop of Q1,

• -I_BR_S – V_BE – 2I_ER_E + VEE  = 0    ———————-(1)

Since I_C = βI_B and I_C ≈ I_E

• I_B ≈ I_E/β                                             ———————-(2)

Substituting (2) in (1)  =>

• – I_ER_S/β – V_BE – 2I_ER_E + VEE  = 0
• – I_E(R_S/β – 2R_E) + VEE – V_BE = 0

Where V_BE = 0.7V for silicon and 0.2V for germanium.

Also R_S/β << 2R_E

Therefore,

• I_E = (VEE – V_BE)/2R_E         ————————(3)

Eqn.(3) =>

• R_E determines the emitter current of Q1 and Q2
• I_E is independent of R_C

Since the voltage drop across R_S is too small, we can neglect it. So,

• V_E = –V_BE
• V_C = VCC – I_CR_C

VCE	= VC – VE
	= (VCC – ICRC) – (–VBE)
	= VCC + VBE – ICRC                  ——————-(4)

We can determine operating point values using equations (3) and (4). Since two transistors are identical, same equations can be used for both.

• I_E = I_C = (VEE – V_BE)/2R_E
• V_CE = VCC + V_BE – I_CR_C

AC Analysis

We can find Voltage Gain Ad and Input Resistance Ri of the differential amplifier by doing AC Analysis. The ac equivalent circuit is obtained by reducing all DC voltage sources to zero and replacing transistor with its equivalent.

Since both dc emitter currents are equal resistances r_e1’ = r_e2’ = r_e’

Applying KVL in loop 1 and 2,

• V_in1 = R_S1i_b1 + i_e1r_e’ + (i_e1 + i_e2)R_E
• V_in2 = R_S2i_b2 + i_e2r_e’ + (i_e1 + i_e2)R_E

We know that,

i_b1 ≈ i_e1/β and i_b2 ≈ i_e2/β

Thus,

• V_in1 = (R_S1/β) i_e1 + i_e1r_e’ + (i_e1 + i_e2) R_E
• V_in2 = (R_S2/β )i_e2 + i_e2r_e’ + (i_e1 + i_e2)R_E

Consider R_S1/ β & R_S2/ β << R_E & r_e’

• V_in1 = i_e1 (r_e’ + R_E) + i_e2 R_E
• V_in2 = i_e2 (r_e’ + R_E) + i_e1R_E

On solving these equations we get,

• i_e1 = (V_in1(r_e’ + R_E) – V_in2R_E )/((r_e’ + R_E)² – R_E²)   ———————(5)
• i_e2 = (V_in2(r_e’ + R_E) – V_in1R_E)/ ((r_e’ + R_E)² – R_E² )  ———————(6)

Voltage Gain

Output voltage, Vo	= VC2 – VC1
	= -RCic2 – (-RCic1) = Rc(ic1 – ic2) => Rc(ie1 – ie2)   —————–(7)

On substituting (5) and (6) in (7) and solving

Vo = (Rc(V_in1 -V_in2)(r_e’ – 2R_E) )/(r_e’(r_e’ + 2R_E))

Vo = (R_C/r_e’)(V_in1 – V_in2)                             ——————————–(8)

Thus the differential gain,  Ad = R_C/r_e’

This proves a differential amplifier amplifies the difference between two input signals.

Differential Input Resistance

Differential Input Resistance is the equivalent resistance measured across either of input terminals and ground. Thus to find out R_i1, V_in2 should be grounded and to measure R_i2, V_in1 should be grounded.

Ri1	= Vin1/ib1 when Vin2 = 0
	= Vin1/(ie1/β)

Substituting equation (5) of i_e1

Ri1	= (Vin1β)/((Vin1(re’ + RE) – Vin2RE )/((re’ + RE)² – RE²))
	= β/((re‘ + RE)/(re‘2 + 2re‘RE)
	= βre‘(re‘ + 2RE)/(re‘ + RE)
	RE >> re‘ re‘ + 2RE ≈ 2RE re‘ + RE ≈ RE
Ri1	= 2βre‘

• R_i1 = 2βr_e‘

Similarly,

• R_i2 = 2βr_e‘

Output resistance

The effective resistance measured at output terminal with respect to ground. So the output resistance is measured between the collector and the ground, which is same as the collector resistance R_C.

• R_O1 = R_O2 = R_C

Common Mode Rejection Ratio (CMRR)

Dual input balanced output differential amplifier should suppress the common signals present at its inputs. A differential amplifier is said to be in common mode when same signal is applied to both inputs and the expected output will be zero, ie ideally common mode gain is zero.

Effectiveness of rejection depends on the matching of two common – emitter stages used. The ability of a differential amplifier to reject common mode signal is called Common Mode Rejection Ratio (CMRR).

CMRR	=|differential gain/common mode gain|
	=|Ad/Ac|
CMRR	Unit of CMRR is dB = 20log|Ad/Ac|

As mentioned earlier, ideally output will be zero in common mode which implies infinite CMRR.